Self-Heating Induced Interchannel Vt Difference of Vertically Stacked Si Nanosheet Gate-All-Around MOSFETs

The natural asymmetry of the vertically stacked channels results in the junction temperature difference in nanosheet channels which is dependent on pitch, nanosheet width, channel number, and input power. The V t difference induced by the self-heating becomes worse with the process imperfections, such as the interface trap density. PFET has higher V t difference due to the higher thermal resistance and stronger temperature dependence of V t than nFET (22mV vs 6.5mV for 15nm pitch, 35nm nanosheet width, 3 channels, and DC input). The V t difference increases with the increasing channel number and nanosheet width.