Low-loss Perforated-Channel HFET

The on-resistance gate capacitance product, RONCG, is an important figure of merit of FET switch characterizing the overall power losses [1, 2]. Decreasing RON by shortening gate-drain spacing decreases the maximum voltage that the power device can operate at and thus typically is not feasible. Reducing RON by increasing the total device width leads to a larger gate capacitance CG, which, in turn, leads to higher switching loss. The same RONCG figure merit relates to the efficiency of microwave power amplifiers, especially those operating in class E, F and other switching modes [3]. We demonstrate a simple and robust perforated channel (PC) HFET design that reduces the onresistance without increasing the total gate capacitance. The reduction of RON is achieved by using the current spreading effect in gate-drain and gate-source regions. Fig. 1(a) shows the schematic of this novel patent pending design for AlGaN/GaN HFET. The portions of the channel under the gate are removed by etching or by any other appropriate technique leaving the channel material in the access regions intact. As a result, the gate channel capacitance decreases. The source and especially the drain side access resistances are significantly smaller than those for the conventional devices with the same CG and continuous channel. As a result, the total device RONCG product is smaller as well. Known solutions like Heterodimensional HFETs [4, 5] FinFET, tri-gate or multi-mesa FETs also use the channel profiling under the gate [6, 7, 8]. However, the channel profiling in these devices is only feasible using nano-scale islands formed in the channel. In contrast, our design is simple and robust; it produces a significant on-resistance reduction using conventional optical lithography process and can be easily implemented in power FET and IC fabrication. 2D simulations of PC-HFET have been performed using Synopsys Sentaurus Device simulator. The HFETs had the channel sheet resistance RSH = 300 Ohm/sq, gate length LG = 1 m; the source-gate distance LSG = 1 m, the gate island width WG = 2 m, the spacing between islands WGG = 1 – 10 m and the gate – drain distance LGD = 1 – 10 m varied in the simulations. The color pattern in Fig. 1(a) shows simulated normalized current density in the PC-HFET channel with WG = 1 m, WGG = 3 m and LGD = 5 m at the drain bias below the knee voltage. As shown by the numbers with arrows, the current density in the G-D spacing within only 1 m off the gate edge reduces almost twice, which indicates a strong current spreading effect in the G-D region. Fig. 1(b) shows simulated PC-HFET G – D region resistance normalized to that of the conventional HFET with the same channel width (i.e. same CG). As seen, at WGG/WG = 3 4, three-four fold RGD reduction is achievable without increasing the HFET capacitance CG. Experimental PC-HFETs have been fabricated on epi-structure consisting of 2 m thick GaN buffer and 20 nm thick Al0.3Ga0.7N barrier grown on sapphire using Migration Enhanced MOCVD (MEMOCVD) technique. Inductively coupled plasma etching was used to define mesa pattern and (a) (b)