RKHS-Methods at Solving Some Radiophysics Problems

Operating speed of digital logic devices depends on type of silicon: PLD, Gate Array or ASIC. FPGAs are the lowest in risk, low in project budget but have the highest cost per unit. Gate Arrays utilize less custom mask making than standard cell and stand in the middle from all of three and fallen from wide use today. Cell based ASICs have the highest performance and lowest cost per unit in case of mass production, but they also have the longest and most expensive design cycle. Also digital designs can be divided on CPU based systems on chip (SoC) and non CPU logic devices. CPU as universal processing unit can solve broad spectrum of various tasks from all areas of human activity. Nevertheless there are exist bottlenecks where CPU can’t satisfy required performance. Usually it happens during implementation of mathematical tasks that require big number of iterations and hence big time expenses to obtain desired result with desired accuracy. To increase efficiency of solving of computational tasks there are used mathematical co-processors. There implemented most efficient ways of computing equations, integrals, differential coefficients. It is obvious that after discovering of new methods of increasing computation accuracy and decreasing computation time it is necessary to re-implement mathematical co-processors or use new generation of IP-cores in PLD, Gate Array, ASIC designs. It is presented, easy to implement as IP-core, method of reduction of computation of certain types of series to exact function that is widely used during calculation of parameters of high radio frequency devices. Presented method decrease computation time of such tasks in tens and hundred times and its inaccuracy is equals to zero.