Fault-tolerance of spaceborne semiconductor mass memories

The architecture of spaceborne Semiconductor Mass Memories is mainly determined by the requirements on reliability and data integrity. The highly granular structure of the memory kernel supports the implementation of hierarchical redundancy structures. Error correcting codes are in use to cope with particle induced bit errors. For protection of 4-bit wide devices an extended Reed-Solomon (78,64) SSC DSD code is appropriate and well suited to a low expenditure H/W implementation of coding and checking.