Modeling and Characterization of Gate Leakage in High-K Metal Gate Technology-Based Embedded DRAM

We report experimental characterization and modeling of direct and trap-assisted tunneling (TAT) in high-K metal gate (HKMG)-based access transistor and deep trench (DT) capacitor constituting a 32 nm embedded dynamic random access memory (eDRAM) device. This is the first eDRAM technology that has successfully integrated HKMG-based access transistor and DT technology. The experimental results are compared with direct and TAT models implemented in a finite element-based device simulator. While in HKMG-based nFET both TAT, and direct tunneling are present, in the DT capacitor TAT is dominant due to higher interface and bulk traps. We demonstrate, through ab initio simulations, that the bulk and interface traps arise due to oxygen vacancies (Ov) in the bulk HfO 2 , and SiO 2 /HfO 2 interface and quantitatively compare direct and TAT currents with experimental results.