HV latchup — Power analog ICs co-design with block level verification

Power Analog ICs which contain both high voltage and low voltages cells require a unique approach to achieve latchup robustness. A methodology was developed to allow both schematic and layout block level latchup verification automation as applied to HV Latchup in Power Analog ICs design. The methodology enables co-design between schematic design and layout design, improving silicon success as well as shortening the design cycle.