SRAM V MIN yield challenge in 40nm embedded NVM process

Embedded non-volatile memory (NVM) introduces additional thermal processes to a logic process flow and the impact from this extra thermal budget becomes more considerable with continued device scaling. This paper investigates the mechanism of SRAM V MIN degradation in a 40nm embedded NVM process and provides a solution to address the degradation caused. Failure analysis shows enlarged poly grain size for SRAM PMOS due to the NVM thermal processes, resulting in a large shift in threshold voltage. The results show that introduction of a p-poly boron pre-dope greatly helps to recover the SRAM V MIN . The mechanism for the V MIN recovery is also explained, with further high-temperature SRAM V MIN studies showing the effectiveness of p-poly pre-dope even at elevated temperatures.