A low power and compact desktop ATM PMD

A PMD sublayer circuit for 25.6 Mb/s ATM interface has been developed in a 0.35 /spl mu/m CMOS process. Although it contains a UTP 100 m cable equalizer circuit and a clock recovery circuit, a low power 74 mW and a small die area 2.52 mm/sup 2/ are achieved. With the circuit, a six port 25.6 Mb/s ATM interface chip has been realized.