A wide-range all digital DLL for multiphase clock generation

This paper presents a wide-range all digital delay-locked loop (DLL) for multiphase clock generation. Using the phase compensation circuit (PCC), the large phase difference is compensated in the initial step. Thus, the proposed solution can overcome the false-lock problem in conventional designs, and keeps the same benefits of conventional DLLs such as good jitter performance and multiphase clock generation. Furthermore, the proposed all digital multiphase clock generator has wide ranges and is not related to specific process. Thus, it can reduce the design time and design complexity in many different applications. The DLL is implemented in a [email protected] CMOS process. The experimental results show that the proposal has a wide frequency range. The peak-to-peak jitter is less than 7.7ps over the operating frequency range of 200MHz-1GHz and the power consumption is 4.8mW at 1GHz. The maximum lock time is 20 clock cycles.