Statistical approach to design DRAM bitcell considering overlay errors

Overlay performance and control requirements have become crucial for achieving high yield and reducing rework process. Increasing discrepancy between hardware solutions and overlay requirements, especially in sub-40nm dynamic random access memory (DRAM) devices, motivates us to study process budgeting techniques and reasonable validation methods. In this paper, we introduce a SMEM (Statistical process Margin Estimation Method) to design the DRAM cell architecture which considers critical dimension (CD) and overlay variations in the perspectives of both cell architecture and manufacturability. We also proposed the method to determine overlay specifications. Using the methodologies, we obtained successfully optimized sub-40 DRAM cells which accurately estimated process tolerances and determined overlay specifications for all layers.