Data cache block release requests

A data processing system includes a processor core that is supported by cache parent and child levels. In response to executing a release command in the processor core, a release request is sent from the processor core to the cache memory of the lower level, wherein the release request specifies a destination address associated with a target cache line. In response to receiving the release request in the cache memory of the child level, it is determined whether the destination address hits in the cache memory of the lower level. In response to determining that the target address hits in the cache memory of the lower level, the target cache line is maintained in a data array of the cache memory of the lower level, and a replacement order field in a directory of the cache memory of the lower level is updated so that the target cache line is adjusted more likely in response to a subsequent cache misses from the cache memory of the lower level.