Low noise, low power dissipation analog LSI electronics for heavy ion detectors

The work performed to date for the Multiplicity-Vertex Detector (MVD) for the PHENIX detector collaboration at the Relativistic Heavy Ion Collider (RHIC) is presented in this paper. Composed of approximately 34,000 channels of both silicon strips and silicon pads, the detector per-channel signal processing chain consists of a preamplifier-gain stage, a current-mode summed multiplicity discriminator, a 64-deep analog memory (simultaneous read-write), an analog correlator and a 10-bit 5 /spl mu/s ADC. All timing control, data buffering, and data formatting for a single 256-channel multi-chip module (MCM) is performed by the system controller or Heap Manager. Each chip set is partitioned into 32-channel sets. Prototype performance for the various blocks will be presented as well as the ionizing radiation damage performance of the 1.2 /spl mu/ nwell CMOS process used for fabrication.