An HDTV Video Decoder IC For ATV Receivers

Obed Duardo,Shining Hsieh,Les Wu,Jonathan Boo,Aditya Khurjekar,Rajesh Hingorani,Paul A. Wilford,Brad Bolton,Hiroyuki Morinaka,Keisuke Okada,Shiro Hosotani,Tadashi Sumi,Paul DaGraca,H. Yamamoto,Tommy Poon

An HDTV Video Decoder IC For ATV Receivers

1997

Obed Duardo
Shining Hsieh
Les Wu
Jonathan Boo
Aditya Khurjekar
Rajesh Hingorani
Paul A. Wilford
Brad Bolton
Hiroyuki Morinaka
Keisuke Okada
Shiro Hosotani
Tadashi Sumi
Paul DaGraca
H. Yamamoto
Tommy Poon

An HDTV video decoder IC for ATV receivers is presented. Its dual decoder architecture supports MPEG-2 MP@HL (62,668,800 display samples per second) and an SDRAM memory bandwidth of 6.5 gigabits per second.

Keywords:

High-definition television
Signal processing
Electronic engineering
Gigabit
Computer science
Circuit design
Architecture
Memory bandwidth
Video decoder
Integrated circuit
Decoding methods

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