Compact modeling and simulation of accelerated circuit aging

Accelerated aging becomes progressively pronounced in various circuits, due to the feedback between circuit operation and aging effects, especially HCI. To predict this behavior, the conventional method requires iterative simulations to track the elevated degradation rate, which is expensive in computation. In this paper, a compact model is derived for accelerated aging. By analyzing the underlying mechanism, the new model connects the degradation rate with both reliability physics and circuit topology. It is compatible with circuit simulation, general for design conditions, and efficient in long-term prediction. The new model is validated by silicon data at 65nm, 28nm, and 16/14nm technologies, demonstrating its scalability and effectiveness. Furthermore, it is applied to several benchmark circuits to illustrate the importance of accelerated aging.