A solder bumping interconnect technology for high-power devices

Modern power semiconductor chips (power MOSFETs and IGBTs) have high current-handling capacities , which are increasingly difficult to realize as modules with conventional bonds. A power ball grid array (PBGA) structure is consequently examined as an alternative. Compared with bonding, it offers advantages such as higher process efficiency, a reduced R/sub DSon/, lower parasitic inductance, better thermal dissipation and thus lower heating of the leads thanks to a larger contact cross-section (De-Shin Liu, and Chin-Yu Ni, 2002). In addition, reliability improvement is expected as against bond contacts in which fatigue is mainly caused by the strongly divergent CTE values of the Si chip (2.6/spl times/10/sup -6/K/sup -1/) and the aluminum bond wire (23.5/spl times/10/sup -6/K/sup -1/). In the PBGA structure presented here, a significantly smaller difference was found between the CTE values of the Si chip and the DCB substrate (7/spl times/10/sup -6/K/sup -1/). To realize a high current-carrying capability, a large number of bumps are connected in parallel for contacting the front of the power semiconductor. The bumps are produced by solder paste printing directly on the copper of the DCB substrate, and the effect of various pattern layouts and solder paste alloys (Pb92.5Sn5Ag2.5 and Pb95Sn5) was examined. A wafer process was developed for producing a solderable front metallization in which the back of the chip is protected by a film. Electrical and thermal characterizations as well as first reliability tests are reported.