Design of Low Power Low Jitter Delay Locked Loop in 45 nm CMOS

The Delay Locked Loop (DLL) are used clock recovery, time interval generation schemes, and time-to-digital conversions. The proposed modified delay cell is used with various PDs and validation is carried for utilizing different applications. The modification in the delay cell is done by shifting its behavior from static to dynamic. Simulation results of DLL implemented in Cadence Virtuoso Schematic Editor using GPDK 45 nm technology have indicated that fast locking with a periodic jitter of 8.84 ps, the phase noise of –82.55 dB/Hz with the Figure of merit (FOM) of 69 has been achieved. The proposed DLL operates in the range of 40–333 MHz with a low power consumption of 0.32 mW from 1.8 V supply. In addition to that, a comparative approach is used. One of them has an ultra-low-power operation, whereas the other one has a low jitter stable operation.