Synthesizable Heterogeneous FPGA Fabrics

We present an automated framework for the generation of synthesizable FPGAs with heterogeneous functional blocks and carry chains, as modelled with the open-source Verilog-to-Routing (VTR) FPGA architecture evaluation framework. VTR's modelling of hardened blocks, such as DSPs and BRAMs, is leveraged to generate synthesizeable FPGAs mappable via VTR's Verilog frontend. The generated Verilog source for the FPGA can be synthesized to target any conventional semiconductor process via an industry-standard ASIC toolflows with minimal implementation effort. We model a Stratix IV-style FPGA architecture, complete with carry chains, DSPs and BRAMs, and compare area/performance with the commercial Stratix IV FPGA. The area and performance gap between the fully synthesizable and commercial fabrics for a set of benchmarks using the heterogeneous blocks is 3.2x and 2.3x, respectively. Optimizations to reduce the gap are discussed.