A Generator of 64~8,192-point FFT/IFFT Cores with Single-memory Architecture for OFDM-based Communication Systems

This paper describes a core generator (FCore_Gen) which generates Verilog-HDL models of 640 different FFT/IFFT cores with selected parameter value for OFDM-based communication systems. The generated FFT/IFFT cores are based on in-place single memory architecture and use a hybrid structure of radix-4 and radix-2 DIF algorithm to accommodate various FFT lengths. To achieve both memory reduction and the improved SQNR, a conditional scaling technique is adopted, which conditionally scales the intermediate results of each computational stage. The cores synthesized with a CMOS standard cell library can operate with 75-MHz@3.3-V, and a 8,192-point FFT can be computed m , thus the cores satisfy the specifications of wireless LAN, DMB, and DVB systems.