FPGA-based accelerator for the scalable underwater acoustic channel emulator

Predicting the performance of underwater acoustic (UWA) communication is a big task because the physical properties of the water. Since sea trial is expensive, prior simulation is a common method to enhance the mission success. However, a simulator cannot predict the real UWA modem performance and behavior. Recently, there is an interest of using an UWA channel emulator for gaining insight of the modem performance under real condition. The emulator mimics the real UWA channel between the transmitter (TX) and receiver (RX). Emulation process can be defined as the convolution between the transmitted signal of UWA modem and UWA channel impulse response (CIR). Consider time-varying and wideband properties of the UWA channel, implementation of convolution can be implemented by using direct-form Finite Impulse Response (FIR) filter and circular buffer. However, implementation of a large number of FIR filter in common personal computer (PC) exponentially increases processing delay. This paper explains the implementation of field-programmable gate array (FPGA) to build a scalable UWA channel emulator.