Evaluating and correcting pattern variability induced by OPC within regular array layout

Over the past few years, patterning edge placement error (EPE) has been established as the key metric for patterning budget generation. In previous work [1] it has been shown that local variability of contact within 28nm node SRAM regular array accounts for more than 90% of total variability. Among the most obvious source of local variability, we can think of optical proximity correction (OPC), mask process, wafer process (litho and etch). If one would like to make breakdown between these sources, process related sources will be very measurement consuming to characterize, and even more complex to correct. On the opposite, OPC can be characterized computationally as well as corrected. Therefore, this paper proposes a computational method to evaluate and correct pattern variability induced by OPC within regular array layout. In a different field of application, array of pixels in imager SoC is very sensitive to pattern variability, especially when it is periodic. This is known as MURA effect, and many works have shown this effect in the field of flat panel display [2]. The challenge is similar in the field of image SoC. Once again, OPC variability is also a contributor to this effect. Therefore, array of pixels is also benefitting from the method proposed in this paper.