Low Power Approximate Multipliers With Truncated Carry Propagation for LSBs

This paper proposes 8$\times$8 bit multiplier architecture which focuses only on the carry generated from first 8 More Significant Bits (MSBs) of the final output. This proposed architecture design is divided into two blocks, one of which maintains accuracy of the design and another block significantly reduces area, power and delay. Three approximate full adders are presented and placed in specific manner to increase the performance of proposed multiplier architecture. Four multipliers using the proposed architecture are simulated in standard CMOS 180 / 65 nm technology node. Maximum delay in the proposed multiplier is 1.04 / 0.42 ns in 180 / 65 nm technology with a total power dissipation of 454.50/ 41.86 $\mu$W respectively. The worst case Power-Delay-Product (PDP) of the proposed multiplier is 422.68 / 15.07 fJ which is 65.5/74.7%less as compared to the conventional (Dadda multiplier) design. In the proposed designs 41.7%less number of transistors are used while in the worst case scenario the normalized error in the output of the proposed designs is 0.0257.