AC stress and standard cell aging characterization to enhance reliability coverage of logic circuits

One of the major purposes of characterizing discrete device reliability is to provide reasonable margin during design phase. Prevention is always better than a cure from risk control and cost management point of view. Over the last decade, foundry has been asked to provide aging aware IP and cell library to reduce customers' product development cycle. Though these libraries were well characterized but their aging behaviors were left to designers' own judgments. To integrate aging effect into static timing analysis (STA) either for synthesis or post-simulation, one needs a fairly accurate SPICE aging model which covers AC stress [1] and gate level (or standard cell level) timing shift. This demands Si-to-Simulation comparisons which will be addressed in this paper.