A process for forming interconnections in a ferroelectric memory device

A process for the preparation of conductive interconnections and of capacitors in a ferroelectric memory device, the method comprising the steps of: Forming a first insulating layer (12) on a semiconductor substrate (10) having a cell array region and a peripheral region; Forming a plurality of contact plugs (14a-e) in the first insulating layer (12) to said semiconductor substrate (10); successively forming a first conductive layer (16), a dielectric layer (17) and a second conductive layer (18) on the first insulating layer (12) and on the contact plugs (14a-e); sequentially etching the second conductive layer (18), the ferroelectric layer (17) and the first conductive layer (16) in this order to form in the cell array region and in the peripheral region, a plurality of capacitor patterns (20, 21, 22), while in the peripheral area at the same time a plurality of first conductive structures (16b, c, d, e, g) are formed from the first conductive layer (16) are structured out; wherein the capacitor structures ...