A 5-bit, 0.08mm2 area flash analog to digital converter implemented on cadence virtuoso 180nm

A 5-bit flash analog to digital converter (ADC) is implemented on 180nm CMOS technology. The ADC is operates at 1.2v and employs best comparator to improve performance of ADC. In this paper implemented two types of comparators, latch type comparator and proposed comparator. Dual input single output differential amplifier as latch stage has been used in proposed comparator. The simulation result of ADC is operating at 5GHz sampling frequency and its delay and power dissipation is 419.9ns and 15.2 mw respectively. At 5GH z the average power dissipation of the encoder circuit is 58.5uw and delay 1.29 ns and proposed comparator delay is 1.1ns.