Stress Memorization Technique—Fundamental Understanding and Low-Cost Integration for Advanced CMOS Technology Using a Nonselective Process

In this paper, a comprehensive work toward the understanding of the stress memorization technique (SMT) is presented. The effects of the SMT upon PMOS and NMOS device performance are investigated and explained. A novel low-cost solution for a maskless SMT integration into advanced CMOS technologies is proposed, and additional device results examining the compatibility of SMT with fully silicided and metal inserted polysilicon gates are presented.