A scalable compact model for III-V heterojunction bipolar transistors

This paper presents a scalable, large signal compact model implemented in Verilog-A and suitable for III-V heterojunction bipolar transistor power amplifiers. It discusses the DC, self-heating, and charge portions of the model and outlines a novel method to scale a parameter set extracted from a single device to the large area arrays typically used in cell phone handset power amplifiers. This method involves a combination of EM simulations of the interconnect manifolds and scaling of the thermal impedances.