Development of wafer level solderball placement process for RDL-first FOWLP

The Fan-out wafer-level packaging technology is an integrated circuit technology as well as an enhancement of standard wafer-level packaging (WLP) solutions. This technology is an attractive packaging approach for mobile applications and heterogeneous integration. It allows better electrical performance, low form factor and at relatively low cost as compared to wafer to wafer stacking or 3D stacked bonding. Furthermore, as the industry moving towards higher density and higher-bandwidth chip to chip interconnections, the application of Package on Package technology offers a solution for applications processors and mobile applications with better thermal and electrical performance. One of the significant advantages of package-on-package FOWLP is the ability of stacking 2 different packages to achieve multi-functionality. However, the overall package has to maintain a low profile for thin portable applications. The work in this paper focus on the development and process of wafer level solderball placement on a molded wafer using RDL-first FOWLP process. The Fanout molded wafer is 0.47mm thick and the package size is after singulation. The work in this paper focus on the development and process of wafer level solderball placement on a molded wafer using RDL-first FOWLP process. The Fanout molded wafer is 0.47mm thick and the package size is $15 \times 15\ \mathbf{mm}^{2}$ after singulation. Detailed process parameters on flux printing process parameters such as the printing speed and printing gap coupled with ball placement speed, ball dispense gap and ball head moving direction needs to be evaluated to achieve robust wafer level solderball placement process with good flux printing and good ball placement process yield.