An 8.6 um2 cell technology for a 35.5 mm2 megabit EPROM

A one megabit CMOS EPROM with a Floating gate Avalanche injection MOS (FAMOS) cell area of 8.6 µm 2 has been fabricated at a conservative design rule of 1.2µm This cell, to our knowledge, is the smallest reported EPROM cell. The process utilized an Advanced Contactless EPROM (ACE) technology combined with a High Voltage Enhanced Performance Implanted CMOS (HVEPIC) technology. The combined technique has produced fully functional one MBIT EPROMs with high density (bar size= 35.5 mm 2 of 55 Kmil 2 ) and enhanced performance (130 ns access time) The HVEPIC/ACE technology features twin well CMOS, buried N+ bitlines, ultra-smooth polysilicon floating gates, oxide-nitride-oxide inter-polysilicon dielectric, double level polysilicon, single level metal, self-aligned TiSi2 and a post source/drain anneal processing temperature limited to 800°C.