Analysis of Performance Bottlenecks in SoC Interconnect Subsystems

An interconnect subsystem as a part of SoC most often determines the performance of the entire system, so the analysis of its effectiveness must be started as early as possible. The main point is to determine whether the interconnect subsystem itself is a potential bottleneck. To solve this problem, the following components are important: a test scenario aimed at identifying performance problems, and a methodology for evaluating the results of its execution. This article introduces a new approach to SoC interconnect performance evaluation based on specific test scenarios and a new set of performance metrics and criteria of their evaluation. The basics of proposed approach is to concern the system-level constraints to evaluate interconnect performance.