FABLE-DTS: Hardware-Software Co-Design of a Fast and Stable Data Transmission System for FPGAs

Developers often need collaborative execution between processors and field-programmable gate arrays (FPGAs) to meet resource-intensive computation requirements. Performance of theses collaborative executions depends heavily on the efficiency of simultaneous data movement between multiple FPGAs. Hence, this paper presents a fast and stable data transmission system (FABLE-DTS) to address high-speed data transfer issues in a multi-FPGA environment. First, we design a Dynamic Phase-shift Data Transmission (DPSDTM) hardware module along with a non-linear phase-shift method to obtain an optimal interface timing between two FPGAs. Then, we develop the software framework for processor-FPGA collaboration called DPSDTM-Linux. This framework implements memory buffer allocation and DPSDTM management. After that, a bus bridge module (BBM) is devised to ensure the compatibility of the proposed DTS with different bus types (i.e., AXI and PLB). Finally, we evaluate the system on a custom IC-testing platform consisting of a ZYNQ-7000 SoC and a Virtex-4 FPGA. We find that the proposed FABLE-DTS provides accurate results for transmission tests and FPGA resources tests, demonstrating the stability of the system in intensive computational tasks. Additionally, the proposed design is the fastest FPGA-processor DTS reported to date, supporting up to 368.80MB/s transmission at the clock frequency of the double-data-rate (DDR) interface (i.e., 200MHz).