Chip clock frequency deviation of a spread spectrum system and method for correcting error estimate

The present invention provides a spread spectrum system chip clock frequency error estimation and correction, the receiving antenna receives a radio frequency signal is first converted into a digital baseband signal, followed by a synchronization, the frequency domain interpolation, secondary synchronization, to frequency offset and phase offset, the zero crossing number required to obtain the actual value of the zero crossing, zero crossing by the final number of chips and the corresponding first-order linear relationship over time is 0:00 actual chip clock is obtained, thereby obtaining code chip clock frequency error compensation to achieve frequency and clock correction, to ensure consistent chip clock frequency of a chip clock of the transmitter and receiver to improve demodulation performance of the receiver, the receiver to which the received better recovery The data.