A 500-MHz, 0.4-/spl mu/m CMOS, 32-word by 32-bit 3-port register file

A 0.4-/spl mu/m CMOS, 32-word by 32-bit 3-port register file has been developed for use in high speed microprocessors. It features a high-speed-oriented memory structure, low threshold voltage nMOS FETs, and a short read-precharge design. This register file has been designed for use within a small-skew clock-distribution processor datapath, and experimental results show it to be capable of 500-MHz register file operations.