Comparative Analysis for Performance Evaluation of Full Adders Using Reversible Logic Gates

Reversible logic is becoming more prominent logic for Power and Delay optimization. From last few years it has been incorporated in number of applications such as Bioinformatics, Quantum computing, DNA computing, Nanotechnology and low power VLSI. In Conventional digital circuits, the main cause of power dissipation is the disposal of bits of information while the logical operations are being carried out, So if these circuits are designed with reversible logic, the bit loss can be preserved. As 1-bit Full Adder is the elementary unit in almost all the digital circuits, So this paper gives the Comparative Analysis of 1 bit Full Adder circuit using reversible logic in order to find out the most efficient circuit in comparison to existing ones as in terms of Dynamic Power, Leakage Power, Area and Delay. All the circuits were designed with Verilog HDL and has been simulated Using NC-SIM. The RTL analysis was carried out with RTL compiler 14.01 by Cadence for Power, Area and Delay at 90nm and 45nm technology for both fast and slow library.