Implementation of Encryption Algorithm and Wireless Image Transmission System on FPGA

In this paper, we proposed to improve bit insertion based on the common chaotic encryption algorithm, which reduces the computational complexity of the chaotic encryption algorithm and is used on low computational systems. We changed the encryption steps from permutation to XOR and XOR to bit insertion, which is our proposed bitwise operation based on encryption. Next, we proposed a four-dimensional chaotic system using the discrete time signal of the chaotic system for the key generator and optimized the floating point operation as well as FPGA resources of the chaotic system. Then, we implemented the algorithm on our Nios II-based wireless image transmission system, where the system’s processor clock is 50 MHz. Finally, we performed a security analysis on our encryption algorithm, and the results show that our proposed algorithm consumes less computing resources while maintaining sufficient security.