저전력 전압정류기를 이용한 디스플레이포트용 2㎃ 1.35㎓ 위상고정루프

A low-power 1.35GHz phase-locked loop in 0.13um CMOS process is proposed for the DisplayPort application. The PLL generates 8 multi-phase clocks for the DisplayPort transceiver and it consumes only 2㎃, which makes it highly suitable for low-power applications. It adopts the supply voltage regulation technique in the VCO to reduce the power supply induced noise. The rms jitter was measured to be the 4.64ps, which is 0.63% of the period. The PLL occupies 0.155㎟.