BEOL lithography for early development at the 65-nm node

This paper will present results obtained during the early development of a lithography process to meet the requirements of the 65 nm node in the BEOL. For the metal levels, an IBM/JSR jointly developed trench level resist was characterized and implemented. Resist image profile, process window, through pitch performance, image shortening and the effect of illumination conditions are discussed. Results from focus - exposure monitor (FEM) wafers are shown which were characterized for minimum resolution, process window and electrical continuity through a maze structure. For the via levels, results from another IBM/JSR jointly developed resist with high resolution and process windows are described. Process windows for nested and isolated vias are given, as well as results showing the improvement in process window and resolution due to the ARC etch. The results also include FEM measurements showing the electrical continuity through simple via chain structures versus the dimension of the via.