Design and Implementation of a New Digital,High-Precision,Fast Pseudo-Code Capture and Delayed Locking Loop

This paper describes the design and FPGA implementation of a new full parallel,fast capturing and delayed locking loop.The capture time is less than or equal to one pseudo-code period and the antijamming tolerance is larger than 80 dB.The fast capture and delayed locking loop achieves full parallel capture and the high accuracy tracking in 127 loops,and it is required only to memorize 130 PN code lists(that are approximately 1/3 of those for other parallel capture delayed locking loops or series-parallel loops),and provides higher capture accuracies than other loops.