Effects of ZrO 2 /Al 2 O 3 Gate-Stack on the Performance of Planar-Type InGaAs TFET

We investigate the impact of gate-stack engineering using W/ZrO 2 /Al 2 O 3 on the performance of planar-type InGaAs tunneling field-effect transistors (TFETs). It is shown that 1-nm-thick capacitance equivalent thickness (CET) with low leakage current is achieved by using ZrO 2 with the dielectric constant of around 40 on In 0.53 Ga 0.47 As. On the other hand, the reduction of D it by insertion of ALD 1–5 cycle Al 2 O 3 interfacial layers (ILs) is found to be mandatory for obtaining TFET performance enhancement. The planar-type InGaAs TFETs using the ZrO 2 /Al 2 O 3 IL gate-stack with CET of 1 nm exhibit the minimum subthreshold swing (S. $\text{S}_{\min }$ ) of 55 mV/dec and ${I}_{ \mathrm{\scriptscriptstyle ON}}$ of $0.88~\mu \text{A}/\mu \text{m}$ ( ${V}_{\text {G}}$ – ${V}_{ \mathrm{\scriptscriptstyle OFF}}= \text {0.5}$ V, ${V}_{\text {D}}= \text {0.2}$ V, and ${I}_{ \mathrm{\scriptscriptstyle OFF}}= \text {10}$ pA/ $\mu \text{m}$ ). Furthermore, the ZrO 2 /Al 2 O 3 IL gate-stack is applied to the optimized In 0.75 Ga 0.25 As quantum well (QW) channel TFETs. The low S. $\text{S}_{\min }$ of 50 mV/dec and high ${I}_{ \mathrm{\scriptscriptstyle ON}}$ of $1.2~\mu \text{A}/\mu \text{m}$ ( ${V}_{\text {G}}$ – ${V}_{ \mathrm{\scriptscriptstyle OFF}}= \text {0.5}$ V, ${V}_{\text {D}}= \text {0.2}$ V, ${I}_{ \mathrm{\scriptscriptstyle OFF}}= \text {10}$ pA/ $\mu \text{m}$ , and CET = 1.1 nm) are demonstrated by combing the present ZrO 2 -based gate-stack with the optimum In 0.75 Ga 0.25 As QW channel structure.