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Modeling and Analysis of Bus Contention for Hardware Accelerators in FPGA SoCs (Artifact).
Modeling and Analysis of Bus Contention for Hardware Accelerators in FPGA SoCs (Artifact).
2020
Francesco Restuccia
Marco Pagani
Alessandro Biondi
Mauro Marinoni
Giorgio Buttazzo
Keywords:
Bus contention
Field-programmable gate array
Computer hardware
Computer science
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