Low power embedded DRAM using 0.6V super retention mode with word line data mirroring

An 88% reduction of refresh power of the 65nm embedded DRAM is achieved using Super Retention Mode (SRM) with Word Line Data Mirroring(WLDM). The retention time in Super Retention Mode is measured in the range of 0.55V to 1.2V. The minimum refresh power is obtained at 0.6V. The retention time of Super Retention Mode at 0.6V is extended by 4.1 times from that of conventional single cell operation at 1.2V. The transition time from normal mode to Super Retention Mode of 22.6μs is achieved with only 0.4% area penalty.