Integrated circuit device and storage system with data buffer and control method thereof

Integrated circuit package with - a data buffer (800, 900) and - a data width control circuit (100, 200, 300) for selectively controlling a data width of the data buffer (800, 900) in response to an external address signal (ADDR ), wherein the data width control circuit (100, 200, 300) comprises the following components : - a decoder (100) for decoding the external address signal (ADDR ) and for generating a first control signal in response to a data read command (READ) or a data write command (WRITE), - a data input buffer control circuit (300) which is activated in response to the data write command (WRITE), and generates a second control signal for controlling the data width of the data input buffer (900) based on the first control signal, and - a data output buffer control circuit (200) which is activated in response to the data read command (READ) and generates a second control signal for controlling the data width of the data output buffer (800) based on the first control signal.