First integration of Cu TSV using die-to-wafer direct bonding and planarization

Copper-filled Through-Si Vias (TSV) with diameters from 2 µm to 5 µm have been integrated in a die-to-wafer stack combining direct bonding and a planarization technique. TSVs were processed on chip backside after oxide bonding and substrate thinning. The results were compared to the ones achieved with a wafer-to-wafer test vehicle. It was demonstrated that die-to-wafer process developed for this integration does not impact TSV electrical and morphological properties. Moreover, no damage was observed on the stack during TSV process performed at 400°C. This demonstration is the first step to validate the industrial compatibility between high density TSV process and die-to-wafer direct bonding and planarization techniques. With a resistance close to 150 mOhm and a capacitance of about 30 fF, 3 µm-diameter TSV provides excellent electrical performance to heterogeneous 3D ICs.