Soft error hardened voltage bootstrapped Schmitt trigger design for reliable circuits

Abstract Bias Temperature Instability and soft error rate are the major reliability issue with the technology scaling. BTI leads to an increase in the threshold voltage of the MOS transistors, which reduces the drain current. The threshold voltage of the PMOS transistor increases due to NBTI with stress time, which degrades the circuit performance. In this paper, we propose a novel reliable voltage bootstrapped Schmitt trigger circuit with soft error hardening enhancement and lower effect of BTI. We investigate all the circuit simulations which impact on the soft error rate of inverter circuits using HSPICE 65 nm CMOS technology. The results show that the proposed inverter circuit has a higher critical charge and lower soft error rate (SER) when compared to other reference inverter circuits. To better assess, we introduced Vth sensitivity and observed that the degradation of the proposed inverter circuit is 30% higher as compared to conventional CMOS inverter. The proposed inverter offers lower dynamic power, leakage power, and circuit delay of 91.11%, 93.47%, and 38.17%, respectively, as compared to CMOS inverter at 3 years of the stress time. Finally, the overall circuit performance is evaluated using the figure of merits and observes that the proposed inverter has the highest FOM correspond to other inverter circuits, which reveal that the proposed circuit is useful for the applications where the effect of radiations are higher.