Reduction of in-lot overlay variation with integrated metrology, and a holistic control strategy

As DRAM semiconductor manufacturing approaches high volume for 1x nm nodes with immersion lithography, an increased emphasis is being placed on reducing the influence of the systematic wafer-level contribution to the on-product overlay budget. The cost of the needed metrology has hitherto been challenging. However, it will be shown that the availability of fast, accurate diffraction based metrology integrated within the Lithography cluster can enable cost-effective solutions. Together with applications software we will use any relevant context information to optimize control of all exposure-tool actuators during lot processing, to deliver the needed on-product performance. Current process corrections typically are done based on feedback per lot and per exposure chuck. Wafers exposed on the same chuck, belonging to the same lot get exactly the same process corrections. In current HVM processing however, an important contribution to the wafer variation is the differences in processing of the individual wafers. These differences can be related to variations in the usage of the processing tools (e.g. different etch chambers). An extension of the process corrections from chuck-based to process-context based can help in reducing the systematic wafer-level variation. With Integrated Metrology the sampling of wafers through the lot can be adjusted to make sure all different processing-contexts are covered in the measurements. Finally, the impact on Litho process cycle time of the total metrology effort required to enable these performance improvements, will be evaluated, and a proposal will be made on the optimum strategy to enable high-volume manufacturing.