HVM die yield improvement as a function of DRSEM ADC
2010
Given the current manufacturing technology roadmap and the competitiveness of the global semiconductor
manufacturing environment in conjunction with the semiconductor manufacturing market dynamics, the
market place continues to demand a reduced die manufacturing cost. This continuous pressure on lowering
die cost in turn drives an aggressive yield learning curve, a key component of which is defect reduction of
manufacturing induced anomalies. In order to meet and even exceed line and die yield targets there is a
need to revamp defect classification strategies and place a greater emphasize on increasing the accuracy
and purity of the Defect Review Scanning Electron Microscope (DRSEM) Automated Defect Classification
(ADC) results while placing less emphasis on the ADC results of patterned/un-patterned wafer inspection
systems. The increased emphasis on DRSEM ADC results allows for a high degree of automation and
consistency in the classification data and eliminates variance induced by the manufacturing staff.
This paper examines the use of SEM based Auto Defect Classification in a high volume manufacturing
environment as a key driver in the reduction of defect limited yields.
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