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Design of a 2-ns Cycle Time 72-kb ECL-CMOS SRAM Macro
Design of a 2-ns Cycle Time 72-kb ECL-CMOS SRAM Macro
1998
Kazuo Kanetani
Kenichi Ohhata
Takeshi Kusunoki
Hiroaki Nambu
Keywords:
Engineering
Electronic engineering
CMOS
Macro
Static random-access memory
Embedded system
cycle time
Correction
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