A redefinable symbolic simulation technique to testability design rules checking

Symbolic simulation approach is well suited for VLSI design for testability (DFT) rules checking. Unfortunately the existing techniques are not extensible and therefore the verification tools based on them can not be parametrized to follow the evolution of rules. As a solution, a concept of symbolic simulator generator is proposed: both symbolic values and transfer functions of gates are redefinable to cope with different sets of rules and design methodologies. >