Studies of the Stability of Microcrystalline Silicon Bottom-Gate TFTs under Electrical Stress

Studies of the Stability of Microcrystalline Silicon Bottom-Gate TFTs under Electrical Stress Oumkelthoum Moustapha, Alexey Abramov, Y. Bonnassieux and P. Roca i Cabarroca Laboratoire de Physiques des Interfaces et Couches Minces (LPICM), Ecole Polytechnique, CNRS (UMR7647) Route de Saclay 91128 Palaiseau Cedex, France H. Y. Choe Advanced Display Research Center, Kyung Hee University, Seoul 130-701 (Received 24 January 2008) We present, in this paper, the stability results under bias stress of n-type microcrystalline silicon ( c-Si:H) bottomgate thinlm transistors (TFTs) with various intrinsic layer compositions (a single c-Si layer or a dual intrinsic layer made of a-Si:H and c-Si). TFTs were fabricated using the conventional amorphous silicon (a-Si:H) TFT process (low temperature Plasma Enhanced Chemical Vapor Deposition). Our results suggest that the dual layer structure is advantageous in terms of processing while keeping good mobility and stability. After 24 hr of electrical stress the threshold voltage drift ( VT ) was less than 0.2 V and mobility drift ( ) was about 8 %. In order to understand the causes of the instability, experimental analyses were performed; they showed that charge trapping at the interface was responsible for the degradation in the TFTs. Simulation of the impact of threshold voltage (VT ) and the mobility drifts showed that a 1-V variation in VT induced a variation of 36 % in OLED current and that a variation of 20 % in the mobility leads to a 23 % variation in the OLED current. PACS numbers: 85, 73