Source/Drain Engineered Charge-Plasma Junctionless Transistor for the Immune of Line Edge Roughness Effect

In this paper, the charge-plasma structure over the source/drain region is incorporated into a dopingless junctionless transistor for obtaining the superior immunity of line edge roughness (LER). An optimized on/off current ratio is observed by using numerical simulations. It is also demonstrated that the proposed charge-plasma junctionless transistor (CP-JLT) is insensitive to the variation of LER magnitude. We further reveal the physics that LER affects the electrical characteristics of CP-JLT. Channel minimal width position variation and channel width variation are put forward to explore the impact of LER for the first time. It is observed that the LER affects the ${I}_{\text {ON}}$ of CP-JLT due to the changes of the source width caused by channel minimal width position variation, whereas the LER affects the ${I}_{\text {OFF}}$ , SS, and ${V}_{\text {th}}$ mainly through channel width variation. It is thus proved to be a helpful guide to suppress the LER variation of CP-JLT.