Modeling of Potentially Implementable Configurable Logic Block in Quantum Dot Cellular Automata for Nanoelectronic Device Architecture

As the device density of the existing complementary metal oxide semiconductor keeps on increasing to reach its limitations, there is a need for alternative technologies to the existing technology. One such is the quantum dot cellular automata which performs all the operations performed by the CMOS technology. Moreover, it utilizes very low power, less area and high switching speeds. This paper proposes the design and analysis of potentially implementable configurable logic block in quantum dot cellular automata for nanoelectronic device architecture. The proposed design utilizes coplanar wire crossing with five-input majority voter for decoder along with the memory loop for storing the information. The proposed design is validated using the QCA designer tool.